Memory-Based Logic Synthesis - nuovo libro

EAN (ISBN-13): 9781441981035
ISBN (ISBN-10): 1441981039
Copertina rigida
Anno di pubblicazione: 2011
Editore: SPRINGER VERLAG GMBH
201 Pagine
Peso: 0,454 kg
Lingua: eng/Englisch

Libro nella banca dati dal 2009-07-10T20:57:24+02:00 (Rome)
Pagina di dettaglio ultima modifica in 2023-03-01T17:35:48+01:00 (Rome)
ISBN/EAN: 1441981039

ISBN - Stili di scrittura alternativi:
1-4419-8103-9, 978-1-4419-8103-5
Stili di scrittura alternativi e concetti di ricerca simili:
Autore del libro : tsutomu
Titolo del libro: synthesis, memory

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Dati dell'editore

Autore: Tsutomu Sasao
Titolo: Memory-Based Logic Synthesis
Editore: Springer; Springer US
189 Pagine
Anno di pubblicazione: 2011-03-08
New York; NY; US
Stampato / Fatto in
Peso: 1,030 kg
Lingua: Inglese
106,99 € (DE)
109,99 € (AT)
118,00 CHF (CH)
POD
XII, 189 p.

BB; Energy, general; Hardcover, Softcover / Technik/Wärmetechnik, Energietechnik, Kraftwerktechnik; Umwelt; Verstehen; Embedded Systems; FPGA; Integrated Circuit Design; Logic Synthesis; Memory; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Energy Policy, Economics and Management; Electrical Power Engineering; Mechanical Power Engineering; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Elektrotechnik; Energietechnik, Elektrotechnik und Energiemaschinenbau; Schaltkreise und Komponenten (Bauteile); Computer-Aided Design (CAD); BC; EA

This book describes the synthesis of logic functions using memories. It is useful to design field programmable gate arrays (FPGAs) that contain both small-scale memories, called look-up tables (LUTs), and medium-scale memories, called embedded memories.  This is a valuable reference for both FPGA system designers and CAD tool developers, concerned with logic synthesis for FPGAs.  Anyone using logic gates to design logic circuits, you can benefit from the methods described in this book.  Describes in detail the synthesis of logic functions using memories; Introduces a look-up tables (LUT) cascade as a new architecture for logic synthesis; Shows logic design methods for index generation functions; Introduces C-measure, which specifies the complexity of Boolean functions; Introduces hash-based design methods, which efficiently synthesize index generation functions by pairs of smaller memories and can be applied to IP address tables, packet filtering, terminal access controllers, memory patch circuits, virus scanning circuits, intrusion detection circuits, fault map of memories, code converters and pattern matching.