2010, ISBN: 1441909435
This book deals with the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. Widely applied CAD algorithms are evaluated and compared for potential acceleratio… Altro …
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2010, ISBN: 9781441909435
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2010, ISBN: 9781441909435
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2010, ISBN: 9781441909435
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2010, ISBN: 1441909435
This book deals with the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. Widely applied CAD algorithms are evaluated and compared for potential acceleratio… Altro …
Kanupriya Gulati/ Sunil P Khatri:
Hardware Acceleration of Eda Algorithms - edizione con copertina flessibile2010, ISBN: 9781441909435
*Hardware Acceleration of Eda Algorithms* - Custom Ics FPGAs and Gpus. Auflage 2010 / gebundene Ausgabe für 106.99 € / Aus dem Bereich: Bücher, Wissenschaft, Technik Medien > Bücher nein … Altro …
2010
ISBN: 9781441909435
*Hardware Acceleration of Eda Algorithms* - Custom Ics FPGAs and Gpus. Auflage 2010 / gebundene Ausgabe für 106.99 € / Aus dem Bereich: Bücher, Wissenschaft, Technik Medien > Bücher nein … Altro …
2010, ISBN: 9781441909435
2010 Gepflegter, sauberer Zustand. 5974540/2 Versandkostenfreie Lieferung computer-aided design (CAD),micro-alloy transistor, MAT,architecture,algorithms,model,FPGA,static-induction trans… Altro …
2010, ISBN: 9781441909435
[PU: Springer US], Neubindung, Buch fehlerhaft geklebt, Auflage 2010 5974540/12, DE, [SC: 0.00], gebraucht; sehr gut, gewerbliches Angebot, 2010, PayPal, Klarna-Sofortüberweisung, Interna… Altro …
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Informazioni dettagliate del libro - Hardware Acceleration of Eda Algorithms
EAN (ISBN-13): 9781441909435
ISBN (ISBN-10): 1441909435
Copertina rigida
Copertina flessibile
Anno di pubblicazione: 2010
Editore: Springer Nature Singapore
194 Pagine
Peso: 0,469 kg
Lingua: eng/Englisch
Libro nella banca dati dal 2009-08-31T19:52:02+02:00 (Rome)
Pagina di dettaglio ultima modifica in 2024-03-08T17:21:59+01:00 (Rome)
ISBN/EAN: 1441909435
ISBN - Stili di scrittura alternativi:
1-4419-0943-5, 978-1-4419-0943-5
Stili di scrittura alternativi e concetti di ricerca simili:
Autore del libro : sunil, gula, gulat
Titolo del libro: eda, hardware, algorithms, gpu
Dati dell'editore
Autore: Sunil P Khatri; Kanupriya Gulati
Titolo: Hardware Acceleration of EDA Algorithms - Custom ICs, FPGAs and GPUs
Editore: Springer; Springer US
192 Pagine
Anno di pubblicazione: 2010-04-06
New York; NY; US
Stampato / Fatto in
Lingua: Inglese
106,99 € (DE)
109,99 € (AT)
118,00 CHF (CH)
POD
XXII, 192 p.
BB; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; FPGA; Field Programmable Gate Array; algorithms; architecture; computer-aided design (CAD); integrated circuit; micro-alloy transistor, MAT; model; simulation; static-induction transistor; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Computer-Aided Design (CAD); BC
Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. In particular, this book: Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms; Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X; Helps the reader by presenting example algorithmswhich may be used by the reader to determine how best to accelerate their specific EDA algorithm; Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints; Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms.Provides guidelines on whether to use GPUs or FPGAs when accelerating a given EDA algorithm, with validation by a concrete example implemented on both platforms Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups from 30X to 800X Presents techniques in a way that the reader can use example algorithms presented to determine how best to accelerate their specific EDA algorithm Discusses an automatic approach to generate GPU code, given regular uniprocessor code Includes supplementary material: sn.pub/extras
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